Interconnect

An AHB interconnect connects Managers to Subordinates. In a simple single-Manager system, it can be just:

An address decoder.
A Subordinate select signal for each target.
A read-data and response multiplexor.

In a multi-Manager system, the interconnect also performs arbitration and routes address/control/write-data traffic from the selected Manager to the selected Subordinate. The AMBA AHB specification defines the protocol interface behavior; exact arbitration and multi-layer implementation choices are system design decisions.

Address decoding

The decoder examines HADDR and asserts the appropriate HSELx. Each Subordinate has its own select signal.

A Subordinate must only sample HSELx, address, and control when HREADY is HIGH. If HREADY is LOW, the previous data phase is still stalled, and the apparent selected Subordinate can change before the next transfer actually begins.

The minimum address space allocated to a Subordinate is 1KB, and the start and end of the region must be aligned to 1KB boundaries. This matches the burst rule that Managers must not generate incrementing bursts across a 1KB boundary, so a burst cannot cross an address decode boundary.

Default Subordinate

If a system address map is not completely filled, the interconnect must still return a defined response when the Manager accesses an address that does not belong to any real Subordinate. This is the purpose of the default Subordinate.

The decoder selects the default Subordinate when no normal address region matches. The default Subordinate does not represent real memory or a real peripheral. Its job is to complete the transfer cleanly so the bus does not hang.

Multiple Subordinate select

A single Subordinate interface can have multiple HSELx inputs, each representing a different decoded address region. This is useful when one peripheral exposes a main data path and control registers at different locations. The Subordinate interface can be reused without making the Subordinate perform a complex high-order address decode internally.

Read data and response multiplexor

AHB uses a read-data and response multiplexor when a Manager can access two or more Subordinates. The Manager drives address, control, and write data outward through the interconnect. The decoder uses the address phase to decide which Subordinate is selected, and the multiplexor returns only that selected Subordinate’s data-phase response back to the Manager.

In the diagram, each Subordinate has its own response signals, such as HRDATA_x, HRESP_x, and HREADYOUT_x. The multiplexor chooses one set of these signals and drives the shared Manager-facing signals

Interconnect with AHB interfaces

Generic interconnect blocks can offer AHB interfaces on both sides, even if the internal fabric also supports other protocols such as AXI or APB. In this style, the interconnect behaves like an AHB Subordinate to each Manager-facing port and like an AHB Manager to each Subordinate-facing port.

On the Manager-facing side, HTRANS indicates whether the Manager is presenting a valid transfer, and the Manager sees a single HREADY input. That HREADY can be LOW for two different reasons:

Reason HREADY is LOW at the Manager	Meaning
Selected Subordinate inserted wait states	The data phase of the selected transfer has not completed yet.
Interconnect is waiting internally	The transfer is stalled by arbitration or routing inside the interconnect.

On the Subordinate-facing side, the interconnect forwards the transfer type with HTRANS, drives HSEL to indicate that the Subordinate is selected, and supplies an HREADY output. This Subordinate-side HREADY tells the Subordinate whether the previous data phase is still stalled. The Subordinate returns HREADYOUT, and the interconnect passes the selected ready response back toward the Manager side.

AHB Protocol