Transfer Types

HTRANS[1:0] tells the Subordinate whether the current address/control phase represents a real transfer, an idle cycle, or a continuation of a burst.

HTRANS	Type	Meaning
00	IDLE	No data transfer is required.
01	BUSY	Manager is delaying the next beat of a burst.
10	NONSEQ	First beat of a burst or a single transfer.
11	SEQ	Subsequent beat of a burst.

IDLE

A Manager uses IDLE when it has no transfer to perform. Subordinates must ignore IDLE transfers and respond with zero wait-state OKAY behavior. Address and control values during IDLE should not be treated as a real access.

BUSY

BUSY is used inside a burst when the Manager is not ready to continue immediately. It keeps the burst concept alive without requiring a real data beat in that cycle. Subordinates must ignore BUSY transfers and provide a zero wait-state OKAY response.

BUSY is not a general-purpose stall mechanism for arbitrary traffic. Normal data-phase waiting is done through HREADY.

NONSEQ

NONSEQ means the address/control information is unrelated to the previous transfer. A single transfer uses NONSEQ. The first beat of every burst also uses NONSEQ.

SEQ

SEQ means the transfer is a sequential beat of a burst. The address is related to the previous beat, and the control information must remain consistent with the burst rules.

The waveform shows an incrementing read burst using HBURST=INCR. The first real transfer is marked NONSEQ, then the burst continues with SEQ transfers. A BUSY cycle is inserted when the Manager is not ready to issue the next real beat immediately.

Read the waveform in two layers:

The address/control layer is shown by HTRANS, HADDR, HWRITE, and HBURST.
The data/response layer is shown by HREADY and HRDATA.

Because AHB is pipelined, the read data for one address appears during the data phase after that address was issued. For example, address 0x20 is issued with NONSEQ, and its read data appears later as Data (0x20). The same pattern continues for 0x24, 0x28, and 0x2C.

Time	What the waveform shows
T0-T1	The burst starts with a NONSEQ read at address 0x20.
T1-T2	The Manager inserts BUSY, meaning it is still in the burst but not issuing the next real data beat yet. The Subordinate ignores the BUSY transfer.
T2-T3	The burst continues with a SEQ transfer. The address shown is still 0x24, which is the next intended beat after the BUSY cycle.
T3-T4	Another SEQ transfer is issued, now at address 0x28.
T4-T6	The final shown SEQ transfer at address 0x2C is extended because HREADY is LOW for a wait state. The address/control information is held until the transfer can progress.
T6-T7	The burst data phase completes and Data (0x2C) is returned.

The important lesson is that BUSY delays a burst beat without ending the burst, while HREADY delays completion of the current data phase. They are related to timing, but they are not the same mechanism.

Locked transfers

HMASTLOCK indicates that the current transfer is part of a locked sequence. A locked sequence tells the system that the Manager wants the sequence to be treated as indivisible with respect to other competing accesses.

The classic use case is a read-modify-write operation, such as a semaphore update. The Manager reads a location, modifies the value internally, and writes the result back. If another Manager can access the same Subordinate between those two operations, the update might not be atomic. HMASTLOCK gives the interconnect and relevant Subordinate logic a way to preserve the sequence.

The waveform shows a locked read-modify-write sequence with no wait states shown. The Manager first performs a locked read from address A, then performs a locked write back to address A, and finally drives an IDLE transfer after releasing the lock.

Waveform part	What it means
First NONSEQ	Starts the locked sequence with a read transfer. HWRITE is LOW, so address A is read.
Second NONSEQ	Starts a separate write transfer to the same address A. HWRITE is HIGH for this address phase.
HMASTLOCK HIGH	Marks both the read and write as part of one protected sequence. Other Managers must not be allowed to interrupt the protected access to the same shared resource.
HRDATA showing Data (A)	Read data for address A is returned in the read data phase, which overlaps with the next address phase because AHB is pipelined.
HWDATA showing Data (A)	Write data is driven in the write data phase, after the write address phase.
Final IDLE	The Manager releases HMASTLOCK and inserts an idle cycle after the locked sequence, which is the recommended clean ending for a locked transfer sequence.

If a wait state is inserted in a real implementation, the address/control information for the active transfer, including HMASTLOCK, must remain stable until the transfer completes.

Common HTRANS mistakes

Mistake	Result
Driving SEQ for the first beat	Subordinate/interconnect can interpret the burst incorrectly.
Treating BUSY as a valid data access	Subordinate might perform a false read or write.
Changing burst control during SEQ beats	Burst becomes illegal or unpredictable.
Advancing HTRANS while HREADY is LOW	Address/control phase moves before the previous transfer is complete.

AHB Protocol