Signal Description

AHB signals are prefixed with H. The signal set can be understood in groups: global signals, Manager address/control signals, Manager write-data signals, Subordinate response signals, decoder signals, muxed response signals, and optional AHB5 features.

Global signals

Signal	Source	Description
HCLK	Clock source	Bus clock. All protocol timing is related to the rising edge.
HRESETn	Reset controller	Active-low reset. This is the only active-low protocol signal.

Manager-driven signals

A Manager provides address and control information to initiate read and write operations

Signal	Description
HADDR	Byte address of the transfer. Address width is configurable.
HWRITE	Transfer direction. HIGH means write, LOW means read.
HSIZE	Transfer size, such as byte, halfword, word, or wider.
HBURST	Burst type and burst length.
HTRANS	Transfer type: IDLE, BUSY, NONSEQ, or SEQ.
HPROT	Protection and memory attribute information.
HMASTLOCK	Indicates a locked transfer sequence.
HWDATA	Write data driven by the Manager during the data phase.
HWSTRB	Optional write strobes. One bit per write-data byte lane.

Subordinate response signals

A Subordinate responds to transfers initiated by the Manager, using the HSELx select signal from the decoder to determine when to act.

To communicate the transfer’s status back to the Manager, the Subordinate signals:

Status/Extension: Whether the transfer is complete or needs to be extended.
Outcome: Whether the transfer succeeded or failed.

Signal	Description
HRDATA	Read data from the selected Subordinate.
HREADYOUT	Subordinate output that indicates whether its data phase is complete.
HRESP	Transfer response. LOW is OKAY, HIGH is ERROR.

Decoder and muxed interconnect signals

The interconnect component manages the connectivity between Managers and Subordinates. The system architecture scales based on the number of Managers:

Single-Manager Systems: Require only a centralized Decoder and Multiplexor (detailed below).
Multi-Manager Systems: Require an interconnect that handles arbitration and signal routing (address, control, and write data) from multiple Managers to the appropriate Subordinates.

Signal	Description
HSELx	Decoder-generated select signal for a Subordinate.
HREADY	Muxed ready signal returned to the Manager and Subordinates. It is derived from the selected Subordinate response path.

Decoder: Decodes transfer addresses to select the active Subordinate and outputs control signaling to the multiplexor.
Multiplexor: Routes the read data bus and response signals from the selected Subordinate back to the Manager, guided by the decoder’s control signals.

Optional AHB5 signals

These signals are present only when the corresponding interface feature is implemented, such as secure transfers, exclusive transfers, user sideband signaling, or interface protection using parity/check signals.

Signal	Purpose
HNONSEC	Marks Secure or Non-secure transfers when secure transfers are supported.
HEXCL	Marks an exclusive transfer.
HMASTER	Manager identifier used with exclusive transfers.
HEXOKAY	Indicates success or failure of an exclusive transfer.
HAUSER	User-defined request attribute.
HWUSER	User-defined write-data attribute.
HRUSER	User-defined read-data attribute.
HBUSER	User-defined response attribute.
*CHK signals	Optional parity/check signals for interface protection.

Signal width properties

Current AHB specifications describe many signal widths using properties. For example:

Property	Applies to	Practical note
ADDR_WIDTH	HADDR	Commonly 32 bits, but configurable.
DATA_WIDTH	HWDATA, HRDATA	Can be wider than 32 bits in high-bandwidth systems.
HPROT_WIDTH	HPROT	Can be absent, 4 bits, or extended to 7 bits.
HMASTER_WIDTH	HMASTER	Used when exclusive transfer support needs Manager identity.
USER_*_WIDTH	User signals	Width 0 means the signal is not present.

For RTL, treat these as parameters. Do not hard-code 32-bit address or data assumptions unless the local interface contract explicitly fixes those widths.

AHB Protocol