Burst Operation

Bursts allow a Manager to perform multiple related transfers efficiently. A burst can be a single transfer, a fixed-length sequence of 4, 8, or 16 beats, or an undefined-length incrementing sequence. HBURST[2:0] describes which form is being used and how the address changes from beat to beat.

AHB supports two address styles:

Burst style	Address behavior
Incrementing	Each beat address increments by the transfer size indicated by HSIZE.
Wrapping	Each beat address increments by the transfer size, but wraps back to the start of an aligned wrap region.

The first valid beat of a burst is NONSEQ. Later valid beats are SEQ, except when the Manager inserts BUSY cycles between beats.

Burst encoding

HBURST[2:0]	Type	Description
000	SINGLE	Single transfer burst
001	INCR	Incrementing burst of undefined length
010	WRAP4	4-beat wrapping burst
011	INCR4	4-beat incrementing burst
100	WRAP8	8-beat wrapping burst
101	INCR8	8-beat incrementing burst
110	WRAP16	16-beat wrapping burst
111	INCR16	16-beat incrementing burst

The burst size is the number of beats, not the number of bytes. Total data moved by a fixed-length burst is:

number_of_beats * bytes_per_beat_from_HSIZE

For example, an INCR4 burst with HSIZE=010 is four word transfers, so it moves 4 * 4 = 16 bytes. An INCR8 burst with HSIZE=001 is eight halfword transfers, so it moves 8 * 2 = 16 bytes.

Managers can perform a single transfer in either of these ways:

Method	Meaning
HBURST=SINGLE	Explicit single-transfer burst.
HBURST=INCR with one data beat	Undefined-length burst that happens to contain only one beat.

Address generation

For an incrementing burst, each beat address increases by the transfer size. For a 32-bit word INCR4 starting at 0x38, the addresses are:

Beat	Address
0	0x38
1	0x3C
2	0x40
3	0x44

For a wrapping burst, the wrap boundary is:

number_of_beats * bytes_per_beat_from_HSIZE

For a WRAP4 word burst, the wrap region is 4 * 4 = 16 bytes. If the sequence reaches the end of that 16-byte region, the next beat wraps back to the start of the same region. For example, the specification’s WRAP4 word example uses:

Beat	Address
0	0x38
1	0x3C
2	0x30
3	0x34

1KB boundary rule

Managers must not start an incrementing burst that crosses a 1KB address boundary. In practice, burst generation should keep the entire burst inside one 1KB decode region. This keeps address decoding simple because a burst cannot move from one Subordinate address region into another.

All transfers in a burst must also be aligned to the address boundary equal to the transfer size.

For example, word transfers require HADDR[1:0]=00, and

halfword transfers require HADDR[0]=0.

When building a Manager, include checks that prevent illegal boundary-crossing bursts. When building an interconnect or Subordinate, include verification coverage for boundary-near bursts.

BUSY and burst termination

After a burst has started, the Manager can use BUSY transfers if it needs more time before issuing the next real beat. BUSY does not complete a data beat; it only delays burst progress.

Case	Rule
Undefined-length INCR burst	The Manager can insert BUSY transfers and then terminate the burst by moving to IDLE or starting a new NONSEQ transfer.
Fixed-length INCR4, INCR8, INCR16	The burst must not end with BUSY; it must terminate with a SEQ transfer.
Fixed-length WRAP4, WRAP8, WRAP16	The burst must not end with BUSY; it must terminate with a SEQ transfer.
SINGLE burst	A Manager must not perform BUSY immediately after a SINGLE; the next transfer must be IDLE or NONSEQ.

Only undefined-length INCR bursts can effectively use BUSY as the last cycle before terminating the burst.

Early burst termination

Bursts can end early because of an ERROR response or because a multi-layer interconnect terminates access from one Manager so another Manager can use the Subordinate.

Termination source	Required behavior
Subordinate ERROR response	The Manager can cancel the remaining transfers or continue the remaining transfers.
Manager cancels after ERROR	The Manager must drive HTRANS=IDLE during the two-cycle ERROR response.
Incomplete burst after ERROR	The Manager does not have to rebuild or complete the remaining beats later.
Multi-layer interconnect termination	The interconnect can terminate a burst so another Manager can access the Subordinate. The Subordinate must handle the incomplete burst and respond correctly to the next Manager.

The important verification idea is that a Subordinate must respond correctly to the transfer type it sees. It must not assume every fixed-length burst will always complete all beats.

Burst examples

The examples below match the AMBA AHB specification waveform set. You can replace these image files with the corresponding specification diagrams while keeping the tutorial text unchanged.

Example	What to notice
WRAP4 word write	Four beats wrap within a 16-byte region. In the specification example, 0x3C is followed by 0x30.
INCR4 word read	Four beats increment normally. In the specification example, 0x3C is followed by 0x40.
WRAP8 word read	Eight beats wrap within a 32-byte region. In the specification example, 0x3C is followed by 0x20.
INCR8 halfword write	Eight beats increment by two bytes because HSIZE is halfword.
Undefined-length INCR bursts	One burst can end after two halfword writes, and a later burst can start as a separate word read sequence.

4 beat wrapping burst

4 beat incrementing burst

8 beat wrapping burst

8 beat incrementing burst

Undefined length bursts

The first burst is a write consisting of two halfword transfers starting at address 0x20. These transfer addresses increment by two.
The second burst is a read consisting of three word transfers starting at address 0x5C. These transfer addresses increment by four.

AHB Protocol