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Data Bus and Endianness
AHB uses separate write and read data buses:
| Signal | Direction | Phase |
|---|---|---|
| HWDATA | Manager to Subordinate | Write data phase |
| HRDATA | Subordinate to Manager | Read data phase |
The recommended minimum data bus width is 32 bits. The protocol permits 8, 16, 32, 64, 128, 256, 512, and 1024-bit data buses, although 256 bits is enough for most applications.
Write data bus
The Manager drives HWDATA during write transfers. If the transfer is extended, the Manager must hold write data valid until the transfer completes with HREADY HIGH.
For a write narrower than the bus, the Manager only has to drive the active byte lanes. The Subordinate selects the write data from the correct lanes using HADDR, HSIZE, and the system endianness.
Read data bus
The selected Subordinate drives HRDATA during read transfers. If the transfer is extended, the Subordinate only has to provide valid read data in the final cycle of the transfer, when HREADY is HIGH.
For a read narrower than the bus, the Subordinate only has to provide valid data on the active byte lanes. The Manager selects the correct lanes. A Subordinate only needs valid read data when the transfer completes with OKAY; an ERROR response does not require valid HRDATA.
Endianness
Endianness describes how bytes are arranged inside larger data items. AHB supports little-endian and two big-endian styles.
| Endian model | Byte access behavior | Multi-byte behavior |
|---|---|---|
| Little-endian | Byte at an address uses the byte lane selected by that address. | Least significant byte is stored at the transfer address; increasingly significant bytes go to increasing addresses. |
| Byte-invariant big-endian, BE8 | Byte accesses use the same bus byte lane as little-endian for the same address. | Most significant byte is stored at the transfer address; decreasingly significant bytes go to increasing addresses. |
| Word-invariant big-endian, BE32 | Byte accesses can use different bus bits than little-endian or BE8. | Within each word, most significant byte is at the transfer address. For transfers larger than a word, data is split into word-size blocks. |
Endianness examples
Use a 32-bit data bus for the examples below:
| Bus byte lane | Data bits |
|---|---|
| Lane 0 | DATA[7:0] |
| Lane 1 | DATA[15:8] |
| Lane 2 | DATA[23:16] |
| Lane 3 | DATA[31:24] |
For little-endian and BE8 byte accesses, the byte lane is:
Byte_Lane = Address - (INT(Address / Data_Bus_Bytes) x Data_Bus_Bytes)Example byte access at address 0x1002 on a 32-bit bus:
Data_Bus_Bytes = 4
INT(0x1002 / 4) = INT(4098 / 4) = 1024
Byte_Lane = 4098 - (1024 x 4) = 4098 - 4096 = 2
Data bits = DATA[(8 x 2) + 7 : 8 x 2] = DATA[23:16]For BE32 byte accesses, the word-invariant equation reverses the byte lane within each 32-bit word:
Address_Offset = Address - (INT(Address / Data_Bus_Bytes) x Data_Bus_Bytes)
Word_Offset = INT(Address_Offset / 4) x 4
Byte_Offset = Address_Offset - Word_Offset
Byte_Lane = Word_Offset + 3 - Byte_OffsetFor the same byte access at address 0x1002:
Address_Offset = 4098 - (1024 x 4) = 2
Word_Offset = INT(2 / 4) x 4 = 0
Byte_Offset = 2 - 0 = 2
Byte_Lane = 0 + 3 - 2 = 1
Data bits = DATA[(8 x 1) + 7 : 8 x 1] = DATA[15:8]So, for a byte transfer to address 0x1002:
| Endian model | Active byte lane | Active data bits |
|---|---|---|
| Little-endian | 2 | DATA[23:16] |
| BE8 | 2 | DATA[23:16] |
| BE32 | 1 | DATA[15:8] |
Now consider a 32-bit word value 0x11223344 transferred at aligned address 0x1000.
| Byte role in value | Byte value |
|---|---|
| Most significant byte | 0x11 |
| Next byte | 0x22 |
| Next byte | 0x33 |
| Least significant byte | 0x44 |
| Endian model | Address calculation | Byte stored at each address | 32-bit bus layout for the aligned word |
|---|---|---|---|
| Little-endian | LS byte goes to 0x1000; significance increases as address increases. | 0x1000 -> 0x44, 0x1001 -> 0x33, 0x1002 -> 0x22, 0x1003 -> 0x11 | DATA[31:24]=0x11, DATA[23:16]=0x22, DATA[15:8]=0x33, DATA[7:0]=0x44, so the bus bit pattern is 0x11223344. |
| BE8 | MS byte goes to 0x1000; significance decreases as address increases. Byte lanes are still selected like little-endian. | 0x1000 -> 0x11, 0x1001 -> 0x22, 0x1002 -> 0x33, 0x1003 -> 0x44 | Address offsets 0,1,2,3 use lanes 0,1,2,3, so DATA[31:24]=0x44, DATA[23:16]=0x33, DATA[15:8]=0x22, DATA[7:0]=0x11; the bus bit pattern is 0x44332211. |
| BE32 | For a word transfer, MS byte goes to 0x1000 and LS byte goes to 0x1003; the word uses the same MS/LS bus-bit positions as little-endian word transfers. | 0x1000 -> 0x11, 0x1001 -> 0x22, 0x1002 -> 0x33, 0x1003 -> 0x44 | DATA[31:24]=0x11, DATA[23:16]=0x22, DATA[15:8]=0x33, DATA[7:0]=0x44, so the bus bit pattern is 0x11223344. |
For BE32 transfers larger than a word, split the data into 32-bit word blocks. For example, a 64-bit value 0x1122334455667788 has least significant word 0x55667788 and most significant word 0x11223344. In BE32, the least significant word is transferred at the lower address, so bytes from 0x1000 through 0x1007 become 0x55 0x66 0x77 0x88 0x11 0x22 0x33 0x44.
Byte invariance
Byte-invariant big-endian simplifies mixed-endian memory structures because a byte access to a given address uses the same physical byte lane as little-endian. The endianness changes byte order inside multi-byte elements, but individual byte accesses remain invariant. This matters for packet headers, descriptors, and data structures that combine little-endian fields with big-endian payloads.
Data bus width
Real systems often connect different data widths:
- Narrow Subordinate on a wide bus.
- Wide Subordinate on a narrow bus.
- Manager with a wider data path than a target.
The protocol allows the data bus to be 8, 16, 32, 64, 128, 256, 512, or 1024-bits wide. However, it is recommended that a minimum bus width of 32 bits is used. A maximum bus width of 256 bits is adequate for almost all applications.
For a narrow Subordinate on a wide bus, external logic can select the correct half or byte group. Read data can be replicated on multiple parts of the wide bus, or only the required portion can be driven to reduce power. If a Manager attempts a transfer wider than the Subordinate can support, the Subordinate can return ERROR.
For a wide Subordinate on a narrow bus, external logic can split accesses into narrower transfers. For a Manager on a wider bus, the input bus can be multiplexed and the output bus can be replicated. A Manager must not attempt an HSIZE wider than the data bus it connects to unless a limiting or adaptation mechanism exists.
Data bus checklist
| Check | Reason |
|---|---|
| Write data is held until the completing data phase | Prevents wrong-cycle data capture. |
| Read data is meaningful only on OKAY completion | Avoids sampling invalid or error-cycle data. |
| Active byte lanes match HSIZE, HADDR, and endianness | Prevents data corruption. |
| Invalid byte lanes are driven benignly when possible | The spec recommends 0 to avoid data leakage. |
| Width adapters preserve response behavior | Split or merged accesses must still report meaningful errors. |
AHB Protocol